Within integrated circuits, a signal has to propagate through one or more paths consisting of one or more circuit elements as well as through interconnect connecting these circuit elements in a finite amount of time. This finite amount of time is known as the timing budget, and is usually determined by the dock frequency of the system encompassing such path(s). The process of establishing that the propagation delay of a signal or a set of signals falls within the timing budget across a variety of operating voltage, process corner, and temperature conditions is known as timing closure.
An integrated circuit is usually composed of blocks. Blocks in turn are composed of logic and memory elements and basic circuit elements connected by interconnect to perform a desired function. Basic and advanced logic elements are usually built and pre-characterized for a set of loads and operating conditions, and organized in to logic libraries and memory compilers. A segment of interconnect driven by a circuit element and connected to other logic elements or to a final load such as an output pad is referred to as a net. A net can have many active or passive circuit elements connected to it.
Static timing analyzers are utilized to check if a path meets the timing budget. This is done through the summation of delay for each element in a path for the particular interconnect load that the element is driving. Logic libraries have such information pre-characterized and stored through a combination of look-up tables (LUT), equations, and de-rating curves.
FIG. 1 is an exemplary circuit showing basic representation of the aggressor/victim timing problem. The delay of the path extending from the victim input 10 to the victim output 40 is impacted by an aggressor net. This impact is represented by capacitive effect 20. The extent of the impact of the aggressor switching on the delay of the victim path is determined by the difference in phase between the victim and the aggressor 30 and associated net and by the degree of alignment between the two switching signals.
As the size of integrated circuits shrink, the logic and memory elements and basic circuit elements as well as spacing between interconnect elements they contain also shrink. As spacing between interconnect elements shrinks, the impact of capacitive coupling interaction between interconnect elements increases in significance. Accounting for the impact of capacitive coupling interaction in an accurate fashion becomes critical.
FIG. 2A illustrates the impact on the transition of a signal when an aggressor in the immediate vicinity is simultaneously switching in an out-of-phase fashion. The dotted line describes the ideal switching of the signal while the solid line indicates the actual switching and the corresponding timing impact on the transition caused by the switching of the aggressor neighbor. Therefore, timing delay 50 results in the low-to-high transition of the victim circuit due to the aggressor circuit timing and timing delay 60 results in the high-to-low transition of the victim circuit due to the aggressor circuit.
Referring to FIG. 2B, the switching behavior of the victim output in the presence of a capacitively coupled and simultaneously switching aggressor is represented through timing windows 100 and 110 spanning the impact of a fully incident in-phase aggressor to a fully incident out-of-phase aggressor.